Series in Microelectronics
edited by
Wolfgang Fichtner
Qiuting Huang
Heinz Jäckel
Andreas
Schenk
Mathieu Maurice Luisier
Gerhard Tröster
Bernd Witzigmann
Cédric Bessire,
Semiconducting Nanowire Tunnel Devices.
2013. XIV, 146 pages. € 64,00.
ISBN 978-3-86628-471-5
Abstract:
The performance metrics of current microprocessors are severely limited
because of power dissipation restrictions. Further downscaling of the MOSFET
dimensions and operation voltage are pursued to overcome the limits imposed by
heat dissipation. Supply voltage reduction would be the most efficient path but
is limited in a MOSFET by the inverse subthreshold
slope of 60 mV/dec at room
temperature which defines the minimum gate swing possible. Here enters
the Tunnel FET (TFET), which is a new type of transistor that promises to
achieve a steeper turn on slope and therefore would require less voltage swing
to turn the device from on to off and vice versa. Compared to a MOSFET, a
performance advantage is therefore expected at low operation voltage where a
higher current level may be achieved with a lower
overall power dissipation. Towards a high performance TFET, a first study on
all-Si nanowire (NW) tunnel diodes is performed that leads to another material
system, Si-InAs which allows higher tunnel currents
to flow. This hetero-structure is first thoroughly characterized before NW
TFETs based on Si-InAs heterostructures
are fabricated and investigated.
About the Author:
Cédric Bessire was born in Solothurn, Switzerland, in 1985. From 2005 to 2010 he
studied Physics at the Swiss Federal Institute of Technology (ETH) in Z¨ urich and the Ecole Normale Supérieur in Paris. After
having done his Master thesis at the IBM Research Laboratories nearby Zurich,
he started there in late 2010 his PhD studies in collaboration with the
Integrated Systems Laboratory of the ETH Zurich.
Keywords: Halbleiter, Nanodraht, Nanowire, TFET, Esaki, Tunnel, Diode, Si, InAs, Heteroübergang
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