Inh.: Dr. Renate Gorre
Fon: +49 (0)7533 97227
Fax: +49 (0)7533 97228
Series in Microelectronics
edited by Wolfgang
Physical InP-Based HBT Models for
Ultimate Digital Circuit Optimization
2006, XVI, 280 Seiten; € 64,00. ISBN 3-86628-117-X
Physical two-dimensional hydrodynamic (2D HD) models have been developed to simulate the DC and AC characteristics of double heterojunction bipolar transistors (DHBTs) with state-of-the-art accuracy when compared to experimental data. Those DHBTS are vertically and laterally scaled type-I and type-II DHBTs and based on InP (indium phosphide).
For the first time, a physical based device model shows good agreement between simulated and measured circuit data, for example the gate delay of current mode logic (CML) or emitter coupled logic (ECL) ring oscillators of laterally and vertically scaled type-I DHBTs.
The deviation of the simulated gate delays of the digital circuits is smaller than 10%. Additionally, the model successfully predicts the circuit performance of experimental and scaled frequency dividers, multiplexers and drivers. The results represent a significant scientific advancement in the art of physical and scalable HBT modeling.
This thesis provides a needed perspective on the relative impact of device and circuit figures of merit, device design, band structure, breakdown voltage, and material properties on the ultimate performance of practical digital circuits: It will be demonstrated that type-II DHBTs appear to be the most promising technological approach to achieve bit rates towards 300 Gb/s with realistic scaling parameters.
José Miguel Ruiz Palmero received his diploma degree in electrical engineering from the ETH Zurich (Swiss Federal Institute of Technology), in 2002. He was then employed at the Electronics Laboratory of ETH as a research and teaching assistant until 2006. His research interests include ultra-high speed analog and digital circuits, semiconductor device physics and simulations of InP HBTs. He joined A.T. Kearney in 2006 as a management consultant and has already completed several projects amongst others for large European telecommunication companies.
Keywords: Digital Circuit Optimization
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